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mpparse_64.c

/*
 *    Intel Multiprocessor Specification 1.1 and 1.4
 *    compliant MP-table parsing routines.
 *
 *    (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
 *    (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *    Fixes
 *          Erich Boleyn      :     MP v1.4 and additional changes.
 *          Alan Cox    :     Added EBDA scanning
 *          Ingo Molnar :     various cleanups and rewrites
 *          Maciej W. Rozycki:      Bits for default MP configurations
 *          Paul Diefenbaugh: Added full ACPI support
 */

#include <linux/mm.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/acpi.h>
#include <linux/module.h>

#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
#include <asm/pgalloc.h>
#include <asm/io_apic.h>
#include <asm/proto.h>
#include <asm/acpi.h>

/* Have we found an MP table */
int smp_found_config;

/*
 * Various Linux-internal data structures created from the
 * MP-table.
 */
DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };

static int mp_current_pci_id = 0;
/* I/O APIC entries */
struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];

/* # of MP IRQ source entries */
struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];

/* MP IRQ source entries */
int mp_irq_entries;

int nr_ioapics;
unsigned long mp_lapic_addr = 0;



/* Processor that is doing the boot up */
unsigned int boot_cpu_id = -1U;
EXPORT_SYMBOL(boot_cpu_id);

/* Internal processor count */
unsigned int num_processors __cpuinitdata = 0;

unsigned disabled_cpus __cpuinitdata;

/* Bitmask of physically existing CPUs */
physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;

u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };


/*
 * Intel MP BIOS table parsing routines:
 */

/*
 * Checksum an MP configuration block.
 */

static int __init mpf_checksum(unsigned char *mp, int len)
{
      int sum = 0;

      while (len--)
            sum += *mp++;

      return sum & 0xFF;
}

static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
{
      int cpu;
      cpumask_t tmp_map;
      char *bootup_cpu = "";

      if (!(m->mpc_cpuflag & CPU_ENABLED)) {
            disabled_cpus++;
            return;
      }
      if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
            bootup_cpu = " (Bootup-CPU)";
            boot_cpu_id = m->mpc_apicid;
      }

      printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);

      if (num_processors >= NR_CPUS) {
            printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
                  " Processor ignored.\n", NR_CPUS);
            return;
      }

      num_processors++;
      cpus_complement(tmp_map, cpu_present_map);
      cpu = first_cpu(tmp_map);

      physid_set(m->mpc_apicid, phys_cpu_present_map);
      if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
            /*
             * bios_cpu_apicid is required to have processors listed
             * in same order as logical cpu numbers. Hence the first
             * entry is BSP, and so on.
             */
            cpu = 0;
      }
      bios_cpu_apicid[cpu] = m->mpc_apicid;
      /*
       * We get called early in the the start_kernel initialization
       * process when the per_cpu data area is not yet setup, so we
       * use a static array that is removed after the per_cpu data
       * area is created.
       */
      if (x86_cpu_to_apicid_ptr) {
            u8 *x86_cpu_to_apicid = (u8 *)x86_cpu_to_apicid_ptr;
            x86_cpu_to_apicid[cpu] = m->mpc_apicid;
      } else {
            per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid;
      }

      cpu_set(cpu, cpu_possible_map);
      cpu_set(cpu, cpu_present_map);
}

static void __init MP_bus_info (struct mpc_config_bus *m)
{
      char str[7];

      memcpy(str, m->mpc_bustype, 6);
      str[6] = 0;
      Dprintk("Bus #%d is %s\n", m->mpc_busid, str);

      if (strncmp(str, "ISA", 3) == 0) {
            set_bit(m->mpc_busid, mp_bus_not_pci);
      } else if (strncmp(str, "PCI", 3) == 0) {
            clear_bit(m->mpc_busid, mp_bus_not_pci);
            mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
            mp_current_pci_id++;
      } else {
            printk(KERN_ERR "Unknown bustype %s\n", str);
      }
}

static int bad_ioapic(unsigned long address)
{
      if (nr_ioapics >= MAX_IO_APICS) {
            printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
                  "(found %d)\n", MAX_IO_APICS, nr_ioapics);
            panic("Recompile kernel with bigger MAX_IO_APICS!\n");
      }
      if (!address) {
            printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
                  " found in table, skipping!\n");
            return 1;
      }
      return 0;
}

static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
{
      if (!(m->mpc_flags & MPC_APIC_USABLE))
            return;

      printk("I/O APIC #%d at 0x%X.\n",
            m->mpc_apicid, m->mpc_apicaddr);

      if (bad_ioapic(m->mpc_apicaddr))
            return;

      mp_ioapics[nr_ioapics] = *m;
      nr_ioapics++;
}

static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
{
      mp_irqs [mp_irq_entries] = *m;
      Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
            " IRQ %02x, APIC ID %x, APIC INT %02x\n",
                  m->mpc_irqtype, m->mpc_irqflag & 3,
                  (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
                  m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
      if (++mp_irq_entries >= MAX_IRQ_SOURCES)
            panic("Max # of irq sources exceeded!!\n");
}

static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
{
      Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
            " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
                  m->mpc_irqtype, m->mpc_irqflag & 3,
                  (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
                  m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
}

/*
 * Read/parse the MPC
 */

static int __init smp_read_mpc(struct mp_config_table *mpc)
{
      char str[16];
      int count=sizeof(*mpc);
      unsigned char *mpt=((unsigned char *)mpc)+count;

      if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
            printk("MPTABLE: bad signature [%c%c%c%c]!\n",
                  mpc->mpc_signature[0],
                  mpc->mpc_signature[1],
                  mpc->mpc_signature[2],
                  mpc->mpc_signature[3]);
            return 0;
      }
      if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
            printk("MPTABLE: checksum error!\n");
            return 0;
      }
      if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
            printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
                  mpc->mpc_spec);
            return 0;
      }
      if (!mpc->mpc_lapic) {
            printk(KERN_ERR "MPTABLE: null local APIC address!\n");
            return 0;
      }
      memcpy(str,mpc->mpc_oem,8);
      str[8] = 0;
      printk(KERN_INFO "MPTABLE: OEM ID: %s ",str);

      memcpy(str,mpc->mpc_productid,12);
      str[12] = 0;
      printk("MPTABLE: Product ID: %s ",str);

      printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic);

      /* save the local APIC address, it might be non-default */
      if (!acpi_lapic)
            mp_lapic_addr = mpc->mpc_lapic;

      /*
       *    Now process the configuration blocks.
       */
      while (count < mpc->mpc_length) {
            switch(*mpt) {
                  case MP_PROCESSOR:
                  {
                        struct mpc_config_processor *m=
                              (struct mpc_config_processor *)mpt;
                        if (!acpi_lapic)
                              MP_processor_info(m);
                        mpt += sizeof(*m);
                        count += sizeof(*m);
                        break;
                  }
                  case MP_BUS:
                  {
                        struct mpc_config_bus *m=
                              (struct mpc_config_bus *)mpt;
                        MP_bus_info(m);
                        mpt += sizeof(*m);
                        count += sizeof(*m);
                        break;
                  }
                  case MP_IOAPIC:
                  {
                        struct mpc_config_ioapic *m=
                              (struct mpc_config_ioapic *)mpt;
                        MP_ioapic_info(m);
                        mpt += sizeof(*m);
                        count += sizeof(*m);
                        break;
                  }
                  case MP_INTSRC:
                  {
                        struct mpc_config_intsrc *m=
                              (struct mpc_config_intsrc *)mpt;

                        MP_intsrc_info(m);
                        mpt += sizeof(*m);
                        count += sizeof(*m);
                        break;
                  }
                  case MP_LINTSRC:
                  {
                        struct mpc_config_lintsrc *m=
                              (struct mpc_config_lintsrc *)mpt;
                        MP_lintsrc_info(m);
                        mpt += sizeof(*m);
                        count += sizeof(*m);
                        break;
                  }
            }
      }
      setup_apic_routing();
      if (!num_processors)
            printk(KERN_ERR "MPTABLE: no processors registered!\n");
      return num_processors;
}

static int __init ELCR_trigger(unsigned int irq)
{
      unsigned int port;

      port = 0x4d0 + (irq >> 3);
      return (inb(port) >> (irq & 7)) & 1;
}

static void __init construct_default_ioirq_mptable(int mpc_default_type)
{
      struct mpc_config_intsrc intsrc;
      int i;
      int ELCR_fallback = 0;

      intsrc.mpc_type = MP_INTSRC;
      intsrc.mpc_irqflag = 0;             /* conforming */
      intsrc.mpc_srcbus = 0;
      intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;

      intsrc.mpc_irqtype = mp_INT;

      /*
       *  If true, we have an ISA/PCI system with no IRQ entries
       *  in the MP table. To prevent the PCI interrupts from being set up
       *  incorrectly, we try to use the ELCR. The sanity check to see if
       *  there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
       *  never be level sensitive, so we simply see if the ELCR agrees.
       *  If it does, we assume it's valid.
       */
      if (mpc_default_type == 5) {
            printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");

            if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
                  printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
            else {
                  printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
                  ELCR_fallback = 1;
            }
      }

      for (i = 0; i < 16; i++) {
            switch (mpc_default_type) {
            case 2:
                  if (i == 0 || i == 13)
                        continue;   /* IRQ0 & IRQ13 not connected */
                  /* fall through */
            default:
                  if (i == 2)
                        continue;   /* IRQ2 is never connected */
            }

            if (ELCR_fallback) {
                  /*
                   *  If the ELCR indicates a level-sensitive interrupt, we
                   *  copy that information over to the MP table in the
                   *  irqflag field (level sensitive, active high polarity).
                   */
                  if (ELCR_trigger(i))
                        intsrc.mpc_irqflag = 13;
                  else
                        intsrc.mpc_irqflag = 0;
            }

            intsrc.mpc_srcbusirq = i;
            intsrc.mpc_dstirq = i ? i : 2;            /* IRQ0 to INTIN2 */
            MP_intsrc_info(&intsrc);
      }

      intsrc.mpc_irqtype = mp_ExtINT;
      intsrc.mpc_srcbusirq = 0;
      intsrc.mpc_dstirq = 0;                    /* 8259A to INTIN0 */
      MP_intsrc_info(&intsrc);
}

static inline void __init construct_default_ISA_mptable(int mpc_default_type)
{
      struct mpc_config_processor processor;
      struct mpc_config_bus bus;
      struct mpc_config_ioapic ioapic;
      struct mpc_config_lintsrc lintsrc;
      int linttypes[2] = { mp_ExtINT, mp_NMI };
      int i;

      /*
       * local APIC has default address
       */
      mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

      /*
       * 2 CPUs, numbered 0 & 1.
       */
      processor.mpc_type = MP_PROCESSOR;
      processor.mpc_apicver = 0;
      processor.mpc_cpuflag = CPU_ENABLED;
      processor.mpc_cpufeature = 0;
      processor.mpc_featureflag = 0;
      processor.mpc_reserved[0] = 0;
      processor.mpc_reserved[1] = 0;
      for (i = 0; i < 2; i++) {
            processor.mpc_apicid = i;
            MP_processor_info(&processor);
      }

      bus.mpc_type = MP_BUS;
      bus.mpc_busid = 0;
      switch (mpc_default_type) {
            default:
                  printk(KERN_ERR "???\nUnknown standard configuration %d\n",
                        mpc_default_type);
                  /* fall through */
            case 1:
            case 5:
                  memcpy(bus.mpc_bustype, "ISA   ", 6);
                  break;
      }
      MP_bus_info(&bus);
      if (mpc_default_type > 4) {
            bus.mpc_busid = 1;
            memcpy(bus.mpc_bustype, "PCI   ", 6);
            MP_bus_info(&bus);
      }

      ioapic.mpc_type = MP_IOAPIC;
      ioapic.mpc_apicid = 2;
      ioapic.mpc_apicver = 0;
      ioapic.mpc_flags = MPC_APIC_USABLE;
      ioapic.mpc_apicaddr = 0xFEC00000;
      MP_ioapic_info(&ioapic);

      /*
       * We set up most of the low 16 IO-APIC pins according to MPS rules.
       */
      construct_default_ioirq_mptable(mpc_default_type);

      lintsrc.mpc_type = MP_LINTSRC;
      lintsrc.mpc_irqflag = 0;            /* conforming */
      lintsrc.mpc_srcbusid = 0;
      lintsrc.mpc_srcbusirq = 0;
      lintsrc.mpc_destapic = MP_APIC_ALL;
      for (i = 0; i < 2; i++) {
            lintsrc.mpc_irqtype = linttypes[i];
            lintsrc.mpc_destapiclint = i;
            MP_lintsrc_info(&lintsrc);
      }
}

static struct intel_mp_floating *mpf_found;

/*
 * Scan the memory blocks for an SMP configuration block.
 */
void __init get_smp_config (void)
{
      struct intel_mp_floating *mpf = mpf_found;

      /*
       * ACPI supports both logical (e.g. Hyper-Threading) and physical 
       * processors, where MPS only supports physical.
       */
      if (acpi_lapic && acpi_ioapic) {
            printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
            return;
      }
      else if (acpi_lapic)
            printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");

      printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);

      /*
       * Now see if we need to read further.
       */
      if (mpf->mpf_feature1 != 0) {

            printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
            construct_default_ISA_mptable(mpf->mpf_feature1);

      } else if (mpf->mpf_physptr) {

            /*
             * Read the physical hardware table.  Anything here will
             * override the defaults.
             */
            if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
                  smp_found_config = 0;
                  printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
                  printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
                  return;
            }
            /*
             * If there are no explicit MP IRQ entries, then we are
             * broken.  We set up most of the low 16 IO-APIC pins to
             * ISA defaults and hope it will work.
             */
            if (!mp_irq_entries) {
                  struct mpc_config_bus bus;

                  printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");

                  bus.mpc_type = MP_BUS;
                  bus.mpc_busid = 0;
                  memcpy(bus.mpc_bustype, "ISA   ", 6);
                  MP_bus_info(&bus);

                  construct_default_ioirq_mptable(0);
            }

      } else
            BUG();

      printk(KERN_INFO "Processors: %d\n", num_processors);
      /*
       * Only use the first configuration found.
       */
}

static int __init smp_scan_config (unsigned long base, unsigned long length)
{
      extern void __bad_mpf_size(void); 
      unsigned int *bp = phys_to_virt(base);
      struct intel_mp_floating *mpf;

      Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
      if (sizeof(*mpf) != 16)
            __bad_mpf_size();

      while (length > 0) {
            mpf = (struct intel_mp_floating *)bp;
            if ((*bp == SMP_MAGIC_IDENT) &&
                  (mpf->mpf_length == 1) &&
                  !mpf_checksum((unsigned char *)bp, 16) &&
                  ((mpf->mpf_specification == 1)
                        || (mpf->mpf_specification == 4)) ) {

                  smp_found_config = 1;
                  reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
                  if (mpf->mpf_physptr)
                        reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
                  mpf_found = mpf;
                  return 1;
            }
            bp += 4;
            length -= 16;
      }
      return 0;
}

void __init find_smp_config(void)
{
      unsigned int address;

      /*
       * FIXME: Linux assumes you have 640K of base ram..
       * this continues the error...
       *
       * 1) Scan the bottom 1K for a signature
       * 2) Scan the top 1K of base RAM
       * 3) Scan the 64K of bios
       */
      if (smp_scan_config(0x0,0x400) ||
            smp_scan_config(639*0x400,0x400) ||
                  smp_scan_config(0xF0000,0x10000))
            return;
      /*
       * If it is an SMP machine we should know now.
       *
       * there is a real-mode segmented pointer pointing to the
       * 4K EBDA area at 0x40E, calculate and scan it here.
       *
       * NOTE! There are Linux loaders that will corrupt the EBDA
       * area, and as such this kind of SMP config may be less
       * trustworthy, simply because the SMP table may have been
       * stomped on during early boot. These loaders are buggy and
       * should be fixed.
       */

      address = *(unsigned short *)phys_to_virt(0x40E);
      address <<= 4;
      if (smp_scan_config(address, 0x1000))
            return;

      /* If we have come this far, we did not find an MP table  */
       printk(KERN_INFO "No mptable found.\n");
}

/* --------------------------------------------------------------------------
                            ACPI-based MP Configuration
   -------------------------------------------------------------------------- */

#ifdef CONFIG_ACPI

void __init mp_register_lapic_address(u64 address)
{
      mp_lapic_addr = (unsigned long) address;
      set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
      if (boot_cpu_id == -1U)
            boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
}

void __cpuinit mp_register_lapic (u8 id, u8 enabled)
{
      struct mpc_config_processor processor;
      int               boot_cpu = 0;
      
      if (id == boot_cpu_id)
            boot_cpu = 1;

      processor.mpc_type = MP_PROCESSOR;
      processor.mpc_apicid = id;
      processor.mpc_apicver = 0;
      processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
      processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
      processor.mpc_cpufeature = 0;
      processor.mpc_featureflag = 0;
      processor.mpc_reserved[0] = 0;
      processor.mpc_reserved[1] = 0;

      MP_processor_info(&processor);
}

#define MP_ISA_BUS            0
#define MP_MAX_IOAPIC_PIN     127

static struct mp_ioapic_routing {
      int               apic_id;
      int               gsi_start;
      int               gsi_end;
      u32               pin_programmed[4];
} mp_ioapic_routing[MAX_IO_APICS];

static int mp_find_ioapic(int gsi)
{
      int i = 0;

      /* Find the IOAPIC that manages this GSI. */
      for (i = 0; i < nr_ioapics; i++) {
            if ((gsi >= mp_ioapic_routing[i].gsi_start)
                  && (gsi <= mp_ioapic_routing[i].gsi_end))
                  return i;
      }

      printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
      return -1;
}

static u8 uniq_ioapic_id(u8 id)
{
      int i;
      DECLARE_BITMAP(used, 256);
      bitmap_zero(used, 256);
      for (i = 0; i < nr_ioapics; i++) {
            struct mpc_config_ioapic *ia = &mp_ioapics[i];
            __set_bit(ia->mpc_apicid, used);
      }
      if (!test_bit(id, used))
            return id;
      return find_first_zero_bit(used, 256);
}

void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
{
      int idx = 0;

      if (bad_ioapic(address))
            return;

      idx = nr_ioapics;

      mp_ioapics[idx].mpc_type = MP_IOAPIC;
      mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
      mp_ioapics[idx].mpc_apicaddr = address;

      set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
      mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
      mp_ioapics[idx].mpc_apicver = 0;
      
      /* 
       * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
       * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
       */
      mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
      mp_ioapic_routing[idx].gsi_start = gsi_base;
      mp_ioapic_routing[idx].gsi_end = gsi_base + 
            io_apic_get_redir_entries(idx);

      printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
            "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, 
            mp_ioapics[idx].mpc_apicaddr,
            mp_ioapic_routing[idx].gsi_start,
            mp_ioapic_routing[idx].gsi_end);

      nr_ioapics++;
}

void __init
mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32   gsi)
{
      struct mpc_config_intsrc intsrc;
      int               ioapic = -1;
      int               pin = -1;

      /* 
       * Convert 'gsi' to 'ioapic.pin'.
       */
      ioapic = mp_find_ioapic(gsi);
      if (ioapic < 0)
            return;
      pin = gsi - mp_ioapic_routing[ioapic].gsi_start;

      /*
       * TBD: This check is for faulty timer entries, where the override
       *      erroneously sets the trigger to level, resulting in a HUGE 
       *      increase of timer interrupts!
       */
      if ((bus_irq == 0) && (trigger == 3))
            trigger = 1;

      intsrc.mpc_type = MP_INTSRC;
      intsrc.mpc_irqtype = mp_INT;
      intsrc.mpc_irqflag = (trigger << 2) | polarity;
      intsrc.mpc_srcbus = MP_ISA_BUS;
      intsrc.mpc_srcbusirq = bus_irq;                              /* IRQ */
      intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;      /* APIC ID */
      intsrc.mpc_dstirq = pin;                            /* INTIN# */

      Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", 
            intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, 
            (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, 
            intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);

      mp_irqs[mp_irq_entries] = intsrc;
      if (++mp_irq_entries == MAX_IRQ_SOURCES)
            panic("Max # of irq sources exceeded!\n");
}

void __init mp_config_acpi_legacy_irqs(void)
{
      struct mpc_config_intsrc intsrc;
      int i = 0;
      int ioapic = -1;

      /* 
       * Fabricate the legacy ISA bus (bus #31).
       */
      set_bit(MP_ISA_BUS, mp_bus_not_pci);

      /* 
       * Locate the IOAPIC that manages the ISA IRQs (0-15). 
       */
      ioapic = mp_find_ioapic(0);
      if (ioapic < 0)
            return;

      intsrc.mpc_type = MP_INTSRC;
      intsrc.mpc_irqflag = 0;                         /* Conforming */
      intsrc.mpc_srcbus = MP_ISA_BUS;
      intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;

      /* 
       * Use the default configuration for the IRQs 0-15.  Unless
       * overridden by (MADT) interrupt source override entries.
       */
      for (i = 0; i < 16; i++) {
            int idx;

            for (idx = 0; idx < mp_irq_entries; idx++) {
                  struct mpc_config_intsrc *irq = mp_irqs + idx;

                  /* Do we already have a mapping for this ISA IRQ? */
                  if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
                        break;

                  /* Do we already have a mapping for this IOAPIC pin */
                  if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
                        (irq->mpc_dstirq == i))
                        break;
            }

            if (idx != mp_irq_entries) {
                  printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
                  continue;               /* IRQ already used */
            }

            intsrc.mpc_irqtype = mp_INT;
            intsrc.mpc_srcbusirq = i;              /* Identity mapped */
            intsrc.mpc_dstirq = i;

            Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
                  "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, 
                  (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, 
                  intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, 
                  intsrc.mpc_dstirq);

            mp_irqs[mp_irq_entries] = intsrc;
            if (++mp_irq_entries == MAX_IRQ_SOURCES)
                  panic("Max # of irq sources exceeded!\n");
      }
}

int mp_register_gsi(u32 gsi, int triggering, int polarity)
{
      int ioapic = -1;
      int ioapic_pin = 0;
      int idx, bit = 0;

      if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
            return gsi;

      /* Don't set up the ACPI SCI because it's already set up */
      if (acpi_gbl_FADT.sci_interrupt == gsi)
            return gsi;

      ioapic = mp_find_ioapic(gsi);
      if (ioapic < 0) {
            printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
            return gsi;
      }

      ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;

      /* 
       * Avoid pin reprogramming.  PRTs typically include entries  
       * with redundant pin->gsi mappings (but unique PCI devices);
       * we only program the IOAPIC on the first.
       */
      bit = ioapic_pin % 32;
      idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
      if (idx > 3) {
            printk(KERN_ERR "Invalid reference to IOAPIC pin "
                  "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, 
                  ioapic_pin);
            return gsi;
      }
      if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
            Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
                  mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
            return gsi;
      }

      mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);

      io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
            triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
            polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
      return gsi;
}
#endif /*CONFIG_ACPI*/

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