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op_model_p4.c File Reference


Detailed Description

P4 model-specific MSR operations

Remarks:
Copyright 2002 OProfile authors

Read the file COPYING

Author:
Graydon Hoare

Definition in file op_model_p4.c.

#include <linux/oprofile.h>
#include <linux/smp.h>
#include <asm/msr.h>
#include <asm/ptrace.h>
#include <asm/fixmap.h>
#include <asm/apic.h>
#include <asm/nmi.h>
#include "op_x86_model.h"
#include "op_counter.h"

Go to the source code of this file.

Classes

struct  p4_counter_binding
struct  p4_event_binding

Defines

#define CCCR_CLEAR(cccr)   ((cccr) &= CCCR_RESERVED_BITS)
#define CCCR_CLEAR_OVF(cccr)   ((cccr) &= (~(1U<<31)))
#define CCCR_OVF_P(cccr)   ((cccr) & (1U<<31))
#define CCCR_READ(low, high, i)   do {rdmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
#define CCCR_RESERVED_BITS   0x38030FFF
#define CCCR_SET_DISABLE(cccr)   ((cccr) &= ~(1<<12))
#define CCCR_SET_ENABLE(cccr)   ((cccr) |= (1<<12))
#define CCCR_SET_ESCR_SELECT(cccr, sel)   ((cccr) |= (((sel) & 0x07) << 13))
#define CCCR_SET_PMI_OVF_0(cccr)   ((cccr) |= (1<<26))
#define CCCR_SET_PMI_OVF_1(cccr)   ((cccr) |= (1<<27))
#define CCCR_SET_REQUIRED_BITS(cccr)   ((cccr) |= 0x00030000)
#define CCCR_WRITE(low, high, i)   do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
#define CTR_BPU_0   (1 << 0)
#define CTR_BPU_2   (1 << 4)
#define CTR_FLAME_0   (1 << 2)
#define CTR_FLAME_2   (1 << 6)
#define CTR_IQ_4   (1 << 3)
#define CTR_IQ_5   (1 << 7)
#define CTR_IS_RESERVED(msrs, c)   (msrs->counters[(c)].addr ? 1 : 0)
#define CTR_MS_0   (1 << 1)
#define CTR_MS_2   (1 << 5)
#define CTR_OVERFLOW_P(ctr)   (!((ctr) & 0x80000000))
#define CTR_READ(l, h, i)   do {rdmsr(p4_counters[(i)].counter_address, (l), (h));} while (0)
#define CTR_WRITE(l, i)   do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0)
#define CTRL_IS_RESERVED(msrs, c)   (msrs->controls[(c)].addr ? 1 : 0)
#define ESCR_CLEAR(escr)   ((escr) &= ESCR_RESERVED_BITS)
#define ESCR_READ(escr, high, ev, i)   do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
#define ESCR_RESERVED_BITS   0x80000003
#define ESCR_SET_EVENT_MASK(escr, mask)   ((escr) |= (((mask) & 0xffff) << 9))
#define ESCR_SET_EVENT_SELECT(escr, sel)   ((escr) |= (((sel) & 0x3f) << 25))
#define ESCR_SET_OS_0(escr, os)   ((escr) |= (((os) & 1) << 3))
#define ESCR_SET_OS_1(escr, os)   ((escr) |= (((os) & 1) << 1))
#define ESCR_SET_USR_0(escr, usr)   ((escr) |= (((usr) & 1) << 2))
#define ESCR_SET_USR_1(escr, usr)   ((escr) |= (((usr) & 1)))
#define ESCR_WRITE(escr, high, ev, i)   do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
#define MISC_PMC_ENABLED_P(x)   ((x) & 1 << 7)
#define NUM_CCCRS_HT2   9
#define NUM_CCCRS_NON_HT   18
#define NUM_CONTROLS_HT2   (NUM_ESCRS_HT2 + NUM_CCCRS_HT2)
#define NUM_CONTROLS_NON_HT   (NUM_ESCRS_NON_HT + NUM_CCCRS_NON_HT)
#define NUM_COUNTERS_HT2   4
#define NUM_COUNTERS_NON_HT   8
#define NUM_ESCRS_HT2   23
#define NUM_ESCRS_NON_HT   45
#define NUM_EVENTS   39
#define NUM_UNUSED_CCCRS   NUM_CCCRS_NON_HT - NUM_COUNTERS_NON_HT
#define VIRT_CTR(stagger, i)   ((i) + ((num_counters) * (stagger)))

Functions

static int addr_increment (void)
static unsigned int get_stagger (void)
static int p4_check_ctrs (struct pt_regs *const regs, struct op_msrs const *const msrs)
static void p4_fill_in_addresses (struct op_msrs *const msrs)
static void p4_setup_ctrs (struct op_msrs const *const msrs)
static void p4_shutdown (struct op_msrs const *const msrs)
static void p4_start (struct op_msrs const *const msrs)
static void p4_stop (struct op_msrs const *const msrs)
static void pmc_setup_one_p4_counter (unsigned int ctr)
static void setup_num_counters (void)

Variables

static unsigned int num_controls = NUM_CONTROLS_NON_HT
static unsigned int num_counters = NUM_COUNTERS_NON_HT
struct op_x86_model_spec const op_p4_spec
static struct p4_counter_binding p4_counters [NUM_COUNTERS_NON_HT]
static struct p4_event_binding p4_events [NUM_EVENTS]
static unsigned long reset_value [NUM_COUNTERS_NON_HT]


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