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chipcHw_freq chipcHw_setClockFrequency ( chipcHw_CLOCK_e  clock,
uint32_t  freq 
)

Set clock fequency for miscellaneous configurable clocks.

This function sets clock frequency

Returns:
Configured clock frequency in Hz

Definition at line 261 of file chipcHw.c.

References chipcHw_divide(), and chipcHw_getClockFrequency().

Referenced by chipcHw_Init().

      {
      volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
      volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
      volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
      uint32_t vcoFreqPll1Hz = 0;   /* Effective VCO frequency for PLL1 in Hz */
      uint32_t desVcoFreqPll1Hz = 0;      /* Desired VCO frequency for PLL1 in Hz */
      uint32_t vcoFreqPll2Hz = 0;   /* Effective VCO frequency for PLL2 in Hz */
      uint32_t dependentClockType = 0;
      uint32_t vcoHz = 0;
      uint32_t desVcoHz = 0;

      /* Get VCO frequencies */
      if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
            uint64_t adjustFreq = 0;

            vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
                ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);

            /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
            adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
                  (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
                  chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
            vcoFreqPll1Hz += (uint32_t) adjustFreq;

            /* Desired VCO frequency */
            desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
                (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                  chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
      } else {
            vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
                ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
      }
      vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
          ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
           chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);

      switch (clock) {
      case chipcHw_CLOCK_DDR:
            /* Configure the DDR_ctrl:BUS ratio settings */
            {
                  REG_LOCAL_IRQ_SAVE;
                  /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
                  pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
                        << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
                  REG_LOCAL_IRQ_RESTORE;
            }
            pPLLReg = &pChipcHw->DDRClock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_ARM:
            pPLLReg = &pChipcHw->ARMClock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_ESW:
            pPLLReg = &pChipcHw->ESWClock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_VPM:
            /* Configure the VPM:BUS ratio settings */
            {
                  REG_LOCAL_IRQ_SAVE;
                  pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
                        << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
                  REG_LOCAL_IRQ_RESTORE;
            }
            pPLLReg = &pChipcHw->VPMClock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_ESW125:
            pPLLReg = &pChipcHw->ESW125Clock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_UART:
            pPLLReg = &pChipcHw->UARTClock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_SDIO0:
            pPLLReg = &pChipcHw->SDIO0Clock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_SDIO1:
            pPLLReg = &pChipcHw->SDIO1Clock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_SPI:
            pPLLReg = &pChipcHw->SPIClock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_ETM:
            pPLLReg = &pChipcHw->ETMClock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            break;
      case chipcHw_CLOCK_USB:
            pPLLReg = &pChipcHw->USBClock;
            vcoHz = vcoFreqPll2Hz;
            desVcoHz = vcoFreqPll2Hz;
            break;
      case chipcHw_CLOCK_LCD:
            pPLLReg = &pChipcHw->LCDClock;
            vcoHz = vcoFreqPll2Hz;
            desVcoHz = vcoFreqPll2Hz;
            break;
      case chipcHw_CLOCK_APM:
            pPLLReg = &pChipcHw->APMClock;
            vcoHz = vcoFreqPll2Hz;
            desVcoHz = vcoFreqPll2Hz;
            break;
      case chipcHw_CLOCK_BUS:
            pClockCtrl = &pChipcHw->ACLKClock;
            pDependentClock = &pChipcHw->ARMClock;
            vcoHz = vcoFreqPll1Hz;
            desVcoHz = desVcoFreqPll1Hz;
            dependentClockType = PLL_CLOCK;
            break;
      case chipcHw_CLOCK_OTP:
            pClockCtrl = &pChipcHw->OTPClock;
            break;
      case chipcHw_CLOCK_I2C:
            pClockCtrl = &pChipcHw->I2CClock;
            break;
      case chipcHw_CLOCK_I2S0:
            pClockCtrl = &pChipcHw->I2S0Clock;
            break;
      case chipcHw_CLOCK_RTBUS:
            pClockCtrl = &pChipcHw->RTBUSClock;
            pDependentClock = &pChipcHw->ACLKClock;
            dependentClockType = NON_PLL_CLOCK;
            break;
      case chipcHw_CLOCK_APM100:
            pClockCtrl = &pChipcHw->APM100Clock;
            pDependentClock = &pChipcHw->APMClock;
            vcoHz = vcoFreqPll2Hz;
            desVcoHz = vcoFreqPll2Hz;
            dependentClockType = PLL_CLOCK;
            break;
      case chipcHw_CLOCK_TSC:
            pClockCtrl = &pChipcHw->TSCClock;
            break;
      case chipcHw_CLOCK_LED:
            pClockCtrl = &pChipcHw->LEDClock;
            break;
      case chipcHw_CLOCK_I2S1:
            pClockCtrl = &pChipcHw->I2S1Clock;
            break;
      }

      if (pPLLReg) {
            /* Select XTAL as bypass source */
            reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
            reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
            /* For DDR settings use only the PLL divider clock */
            if (pPLLReg == &pChipcHw->DDRClock) {
                  /* Set M1DIV for PLL1, which controls the DDR clock */
                  reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
                  /* Calculate expected frequency */
                  freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
            } else {
                  /* From chip revision number B0, LCD clock is internally divided by 2 */
                  if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
                        desVcoHz >>= 1;
                        vcoHz >>= 1;
                  }
                  /* Set MDIV to change the frequency */
                  reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
                  reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
                  /* Calculate expected frequency */
                  freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
            }
            /* Wait for for atleast 200ns as per the protocol to change frequency */
            udelay(1);
            /* Do not bypass */
            reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
            /* Return the configured frequency */
            return freq;
      } else if (pClockCtrl) {
            uint32_t divider = 0;

            /* Divider clock should not be bypassed  */
            reg32_modify_and(pClockCtrl,
                         ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);

            /* Identify the clock source */
            if (pDependentClock) {
                  switch (dependentClockType) {
                  case PLL_CLOCK:
                        divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
                        break;
                  case NON_PLL_CLOCK:
                        {
                              uint32_t sourceClock = 0;

                              if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
                                    sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                              } else {
                                    uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                    sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
                              }
                              divider = chipcHw_divide(sourceClock, freq);
                        }
                        break;
                  }
            } else {
                  divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
            }

            if (divider) {
                  REG_LOCAL_IRQ_SAVE;
                  /* Set the divider to obtain the required frequency */
                  *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
                  REG_LOCAL_IRQ_RESTORE;
                  return freq;
            }
      }

      return 0;
}

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