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int chipcHw_vpmPhaseAlign ( void   )

Set VPM clock in sync with BUS clock.

This function does the phase adjustment between VPM and BUS clock

Returns:
>= 0 : On success (# of adjustment required) -1 : On failure

Definition at line 689 of file chipcHw.c.

References vpmPhaseAlignA0().

{

      if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
            return vpmPhaseAlignA0();
      } else {
            uint32_t phaseControl = chipcHw_getVpmPhaseControl();
            uint32_t phaseValue = 0;
            int adjustCount = 0;

            /* Disable VPM access */
            pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
            /* Disable HW VPM phase alignment  */
            chipcHw_vpmHwPhaseAlignDisable();
            /* Enable SW VPM phase alignment  */
            chipcHw_vpmSwPhaseAlignEnable();
            /* Adjust VPM phase */
            while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
                  phaseValue = chipcHw_getVpmHwPhaseAlignStatus();

                  /* Adjust phase control value */
                  if (phaseValue > 0xF) {
                        /* Increment phase control value */
                        phaseControl++;
                  } else if (phaseValue < 0xF) {
                        /* Decrement phase control value */
                        phaseControl--;
                  } else {
                        /* Enable VPM access */
                        pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
                        /* Return adjust count */
                        return adjustCount;
                  }
                  /* Change the value of PH_CTRL. */
                  reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                  /* Wait atleast 20 ns */
                  udelay(1);
                  /* Toggle the LOAD_CH after phase control is written. */
                  pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
                  /* Count adjustment */
                  adjustCount++;
            }
      }

      /* Disable VPM access */
      pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
      return -1;
}

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