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int dmacHw_configChannel ( dmacHw_HANDLE_t  handle,
dmacHw_CONFIG_t pConfig 
)

Configure DMA channel.

Returns:
0 : On success -1 : On failure

Definition at line 450 of file dmacHw.c.

References dmacHw_GetTrWidthInBytes().

      {
      dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
      uint32_t cfgHigh = 0;
      int srcTrSize;
      int dstTrSize;

      pCblk->varDataStarted = 0;
      pCblk->userData = NULL;

      /* Configure
         - Burst transaction when enough data in available in FIFO
         - AHB Access protection 1
         - Source and destination peripheral ports
       */
      cfgHigh =
          dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
          dmacHw_SRC_PERI_INTF(pConfig->
                         srcPeripheralPort) |
          dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
      /* Set priority */
      dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
                            pConfig->channelPriority);

      if (pConfig->dstStatusRegisterAddress != 0) {
            /* Destination status update enable */
            cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
            /* Configure status registers */
            dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
                           pConfig->dstStatusRegisterAddress);
      }

      if (pConfig->srcStatusRegisterAddress != 0) {
            /* Source status update enable */
            cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
            /* Source status update enable */
            dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
                           pConfig->srcStatusRegisterAddress);
      }
      /* Configure the config high register */
      dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;

      /* Clear all raw interrupt status */
      dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
      dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
      dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);

      /* Configure block interrupt */
      if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
            dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
      } else {
            dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
      }
      /* Configure complete transfer interrupt */
      if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
            dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
      } else {
            dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
      }
      /* Configure error interrupt */
      if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
            dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
      } else {
            dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
      }
      /* Configure gather register */
      if (pConfig->srcGatherWidth) {
            srcTrSize =
                dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
            if (!
                ((pConfig->srcGatherWidth % srcTrSize)
                 && (pConfig->srcGatherJump % srcTrSize))) {
                  dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
                      ((pConfig->srcGatherWidth /
                        srcTrSize) << 20) | (pConfig->srcGatherJump /
                                       srcTrSize);
            } else {
                  return -1;
            }
      }
      /* Configure scatter register */
      if (pConfig->dstScatterWidth) {
            dstTrSize =
                dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
            if (!
                ((pConfig->dstScatterWidth % dstTrSize)
                 && (pConfig->dstScatterJump % dstTrSize))) {
                  dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
                      ((pConfig->dstScatterWidth /
                        dstTrSize) << 20) | (pConfig->dstScatterJump /
                                       dstTrSize);
            } else {
                  return -1;
            }
      }
      return 0;
}

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