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Classes | Defines | Typedefs | Enumerations | Functions

dmacHw.h File Reference

API definitions for low level DMA controller driver. More...

#include <stddef.h>
#include <csp/stdint.h>
#include <mach/csp/dmacHw_reg.h>
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Classes

struct  dmacHw_CONFIG_t

Defines

#define dmacHw_MAKE_CHANNEL_ID(m, c)   (m << 8 | c)

Typedefs

typedef unsigned long dmacHw_HANDLE_t
typedef uint32_t dmacHw_ID_t

Enumerations

enum  dmacHw_ADDRESS_UPDATE_MODE_e {
  dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,
  dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC
}
enum  dmacHw_BURST_WIDTH_e {
  dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,
  dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16
}
enum  dmacHw_CHANNEL_PRIORITY_e {
  dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,
  dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7
}
enum  dmacHw_CONTROLLER_ATTRIB_e {
  dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,
  dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE
}
enum  dmacHw_FLOW_CONTROL_e { dmacHw_FLOW_CONTROL_DMA, dmacHw_FLOW_CONTROL_PERIPHERAL }
enum  dmacHw_INTERRUPT_e { dmacHw_INTERRUPT_DISABLE, dmacHw_INTERRUPT_ENABLE }
enum  dmacHw_INTERRUPT_STATUS_e { dmacHw_INTERRUPT_STATUS_NONE = 0x0, dmacHw_INTERRUPT_STATUS_TRANS = 0x1, dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, dmacHw_INTERRUPT_STATUS_ERROR = 0x4 }
enum  dmacHw_MASTER_INTERFACE_e { dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 }
enum  dmacHw_TRANSACTION_WIDTH_e {
  dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,
  dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64
}
enum  dmacHw_TRANSFER_MODE_e { dmacHw_TRANSFER_MODE_PERREQUEST, dmacHw_TRANSFER_MODE_CONTINUOUS, dmacHw_TRANSFER_MODE_PERIODIC }
enum  dmacHw_TRANSFER_STATUS_e { dmacHw_TRANSFER_STATUS_BUSY, dmacHw_TRANSFER_STATUS_DONE, dmacHw_TRANSFER_STATUS_ERROR }
enum  dmacHw_TRANSFER_TYPE_e { dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC }

Functions

int dmacHw_calculateDescriptorCount (dmacHw_CONFIG_t *pConfig, void *pSrcAddr, void *pDstAddr, size_t dataLen)
 Estimates number of descriptor needed to perform certain DMA transfer.
void dmacHw_clearInterrupt (dmacHw_HANDLE_t handle)
 Clears the interrupt.
int dmacHw_configChannel (dmacHw_HANDLE_t handle, dmacHw_CONFIG_t *pConfig)
 Configure DMA channel.
uint32_t dmacHw_descriptorLen (uint32_t descCnt)
 Finds amount of memory required to form a descriptor ring.
uint32_t dmacHw_descriptorPending (dmacHw_HANDLE_t handle, void *pDescriptor)
 Check the existance of pending descriptor.
void dmacHw_exitDma (void)
 Exit function for DMA.
int dmacHw_freeMem (dmacHw_CONFIG_t *pConfig, void *pDescriptor, void(*fpFree)(void *))
 Deallocates source or destination memory, allocated.
dmacHw_HANDLE_t dmacHw_getChannelHandle (dmacHw_ID_t channelId)
 Gets a handle to a DMA channel.
void * dmacHw_getChannelUserData (dmacHw_HANDLE_t handle)
 Gets channel specific user data.
uint32_t dmacHw_getDmaControllerAttribute (dmacHw_HANDLE_t handle, dmacHw_CONTROLLER_ATTRIB_e attr)
 Provides DMA controller attributes.
dmacHw_HANDLE_t dmacHw_getInterruptSource (void)
 Indentifies a DMA channel causing interrupt.
dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus (dmacHw_HANDLE_t handle)
 Returns the cause of channel specific DMA interrupt.
int dmacHw_initChannel (dmacHw_HANDLE_t handle)
 Initializes a DMA channel for use.
int dmacHw_initDescriptor (void *pDescriptorVirt, uint32_t descriptorPhyAddr, uint32_t len, uint32_t num)
 Initializes descriptor ring.
void dmacHw_initDma (void)
 Initializes DMA.
void dmacHw_initiateTransfer (dmacHw_HANDLE_t handle, dmacHw_CONFIG_t *pConfig, void *pDescriptor)
 Program channel register to initiate transfer.
void dmacHw_printDebugInfo (dmacHw_HANDLE_t handle, void *pDescriptor, int(*fpPrint)(const char *,...))
 Displays channel specific registers and other control parameters.
int dmacHw_readTransferredData (dmacHw_HANDLE_t handle, dmacHw_CONFIG_t *pConfig, void *pDescriptor, void **ppBbuf, size_t *pLlen)
 Read data DMA transferred to memory.
void dmacHw_resetDescriptorControl (void *pDescriptor)
 Resets descriptor control information.
void dmacHw_setChannelUserData (dmacHw_HANDLE_t handle, void *userData)
 Sets channel specific user data.
int dmacHw_setControlDescriptor (dmacHw_CONFIG_t *pConfig, void *pDescriptor, uint32_t ctlAddress, uint32_t control)
 Set descriptor carrying control information.
int dmacHw_setDataDescriptor (dmacHw_CONFIG_t *pConfig, void *pDescriptor, void *pSrcAddr, void *pDstAddr, size_t dataLen)
 Set descriptors for known data length.
int dmacHw_setVariableDataDescriptor (dmacHw_HANDLE_t handle, dmacHw_CONFIG_t *pConfig, void *pDescriptor, uint32_t srcAddr, void *(*fpAlloc)(int len), int len, int num)
 Prepares descriptor ring, when source peripheral working as a flow controller.
void dmacHw_stopTransfer (dmacHw_HANDLE_t handle)
 Program channel register to stop transfer.
dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted (dmacHw_HANDLE_t handle)
 Indicates whether DMA transfer is in progress or completed.

Detailed Description

API definitions for low level DMA controller driver.

Definition in file dmacHw.h.


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