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iomux-mx28.h

/*
 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#ifndef __MACH_IOMUX_MX28_H__
#define __MACH_IOMUX_MX28_H__

#include <mach/iomux.h>

/*
 * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
 * See also iomux.h
 *
 *                                                    BANK  PIN   MUX
 */
/* MUXSEL_0 */
#define MX28_PAD_GPMI_D00__GPMI_D0              MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D01__GPMI_D1              MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D02__GPMI_D2              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D03__GPMI_D3              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D04__GPMI_D4              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D05__GPMI_D5              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D06__GPMI_D6              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_D07__GPMI_D7              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CE0N__GPMI_CE0N                 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CE1N__GPMI_CE1N                 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CE2N__GPMI_CE2N                 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CE3N__GPMI_CE3N                 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDY0__GPMI_READY0               MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDY1__GPMI_READY1               MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDY2__GPMI_READY2               MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDY3__GPMI_READY3               MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RDN__GPMI_RDN             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_WRN__GPMI_WRN             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_ALE__GPMI_ALE             MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_CLE__GPMI_CLE             MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
#define MX28_PAD_GPMI_RESETN__GPMI_RESETN       MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)

#define MX28_PAD_LCD_D00__LCD_D0                MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D01__LCD_D1                MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D02__LCD_D2                MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D03__LCD_D3                MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D04__LCD_D4                MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D05__LCD_D5                MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D06__LCD_D6                MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D07__LCD_D7                MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D08__LCD_D8                MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D09__LCD_D9                MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D10__LCD_D10               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D11__LCD_D11               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D12__LCD_D12               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D13__LCD_D13               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D14__LCD_D14               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D15__LCD_D15               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D16__LCD_D16               MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D17__LCD_D17               MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D18__LCD_D18               MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D19__LCD_D19               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D20__LCD_D20               MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D21__LCD_D21               MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D22__LCD_D22               MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
#define MX28_PAD_LCD_D23__LCD_D23               MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
#define MX28_PAD_LCD_RD_E__LCD_RD_E             MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN               MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
#define MX28_PAD_LCD_RS__LCD_RS                       MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
#define MX28_PAD_LCD_CS__LCD_CS                       MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
#define MX28_PAD_LCD_VSYNC__LCD_VSYNC                 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
#define MX28_PAD_LCD_HSYNC__LCD_HSYNC                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK               MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
#define MX28_PAD_LCD_ENABLE__LCD_ENABLE               MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)

#define MX28_PAD_SSP0_DATA0__SSP0_D0                  MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA1__SSP0_D1                  MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA2__SSP0_D2                  MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA3__SSP0_D3                  MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA4__SSP0_D4                  MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA5__SSP0_D5                  MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA6__SSP0_D6                  MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DATA7__SSP0_D7                  MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_CMD__SSP0_CMD             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT        MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
#define MX28_PAD_SSP0_SCK__SSP0_SCK             MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
#define MX28_PAD_SSP1_SCK__SSP1_SCK             MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
#define MX28_PAD_SSP1_CMD__SSP1_CMD             MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
#define MX28_PAD_SSP1_DATA0__SSP1_D0                  MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
#define MX28_PAD_SSP1_DATA3__SSP1_D3                  MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_SCK__SSP2_SCK             MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_MOSI__SSP2_CMD                  MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_MISO__SSP2_D0             MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_SS0__SSP2_D3              MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_SS1__SSP2_D4              MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
#define MX28_PAD_SSP2_SS2__SSP2_D5              MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
#define MX28_PAD_SSP3_SCK__SSP3_SCK             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
#define MX28_PAD_SSP3_MOSI__SSP3_CMD                  MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
#define MX28_PAD_SSP3_MISO__SSP3_D0             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
#define MX28_PAD_SSP3_SS0__SSP3_D3              MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)

#define MX28_PAD_AUART0_RX__AUART0_RX                 MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
#define MX28_PAD_AUART0_TX__AUART0_TX                 MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
#define MX28_PAD_AUART0_CTS__AUART0_CTS               MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
#define MX28_PAD_AUART0_RTS__AUART0_RTS               MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
#define MX28_PAD_AUART1_RX__AUART1_RX                 MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
#define MX28_PAD_AUART1_TX__AUART1_TX                 MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
#define MX28_PAD_AUART1_CTS__AUART1_CTS               MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
#define MX28_PAD_AUART1_RTS__AUART1_RTS               MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
#define MX28_PAD_AUART2_RX__AUART2_RX                 MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
#define MX28_PAD_AUART2_TX__AUART2_TX                 MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
#define MX28_PAD_AUART2_CTS__AUART2_CTS               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
#define MX28_PAD_AUART2_RTS__AUART2_RTS               MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
#define MX28_PAD_AUART3_RX__AUART3_RX                 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
#define MX28_PAD_AUART3_TX__AUART3_TX                 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
#define MX28_PAD_AUART3_CTS__AUART3_CTS               MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
#define MX28_PAD_AUART3_RTS__AUART3_RTS               MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
#define MX28_PAD_PWM0__PWM_0                    MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
#define MX28_PAD_PWM1__PWM_1                    MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
#define MX28_PAD_PWM2__PWM_2                    MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK               MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK       MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK           MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0           MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
#define MX28_PAD_I2C0_SCL__I2C0_SCL             MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
#define MX28_PAD_I2C0_SDA__I2C0_SDA             MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0           MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
#define MX28_PAD_SPDIF__SPDIF_TX                MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
#define MX28_PAD_PWM3__PWM_3                    MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
#define MX28_PAD_PWM4__PWM_4                    MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
#define MX28_PAD_LCD_RESET__LCD_RESET                 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)

#define MX28_PAD_ENET0_MDC__ENET0_MDC                 MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_MDIO__ENET0_MDIO               MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN       MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RXD0__ENET0_RXD0               MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RXD1__ENET0_RXD1               MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK           MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN       MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TXD0__ENET0_TXD0               MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TXD1__ENET0_TXD1               MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RXD2__ENET0_RXD2               MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RXD3__ENET0_RXD3               MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TXD2__ENET0_TXD2               MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_TXD3__ENET0_TXD3               MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK           MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_COL__ENET0_COL                 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
#define MX28_PAD_ENET0_CRS__ENET0_CRS                 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
#define MX28_PAD_ENET_CLK__CLKCTRL_ENET               MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
#define MX28_PAD_JTAG_RTCK__JTAG_RTCK                 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)

#define MX28_PAD_EMI_D00__EMI_DATA0             MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D01__EMI_DATA1             MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D02__EMI_DATA2             MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D03__EMI_DATA3             MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D04__EMI_DATA4             MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D05__EMI_DATA5             MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D06__EMI_DATA6             MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D07__EMI_DATA7             MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D08__EMI_DATA8             MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D09__EMI_DATA9             MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D10__EMI_DATA10                  MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D11__EMI_DATA11                  MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D12__EMI_DATA12                  MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D13__EMI_DATA13                  MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D14__EMI_DATA14                  MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
#define MX28_PAD_EMI_D15__EMI_DATA15                  MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
#define MX28_PAD_EMI_ODT0__EMI_ODT0             MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DQM0__EMI_DQM0             MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
#define MX28_PAD_EMI_ODT1__EMI_ODT1             MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DQM1__EMI_DQM1             MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK     MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CLK__EMI_CLK               MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DQS0__EMI_DQS0             MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DQS1__EMI_DQS1             MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN           MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)

#define MX28_PAD_EMI_A00__EMI_ADDR0             MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A01__EMI_ADDR1             MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A02__EMI_ADDR2             MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A03__EMI_ADDR3             MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A04__EMI_ADDR4             MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A05__EMI_ADDR5             MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A06__EMI_ADDR6             MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A07__EMI_ADDR7             MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A08__EMI_ADDR8             MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A09__EMI_ADDR9             MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A10__EMI_ADDR10                  MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A11__EMI_ADDR11                  MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A12__EMI_ADDR12                  MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A13__EMI_ADDR13                  MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
#define MX28_PAD_EMI_A14__EMI_ADDR14                  MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
#define MX28_PAD_EMI_BA0__EMI_BA0               MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
#define MX28_PAD_EMI_BA1__EMI_BA1               MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
#define MX28_PAD_EMI_BA2__EMI_BA2               MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CASN__EMI_CASN             MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
#define MX28_PAD_EMI_RASN__EMI_RASN             MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
#define MX28_PAD_EMI_WEN__EMI_WEN               MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CE0N__EMI_CE0N             MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CE1N__EMI_CE1N             MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
#define MX28_PAD_EMI_CKE__EMI_CKE               MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)

/* MUXSEL_1 */
#define MX28_PAD_GPMI_D00__SSP1_D0              MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D01__SSP1_D1              MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D02__SSP1_D2              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D03__SSP1_D3              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D04__SSP1_D4              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D05__SSP1_D5              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D06__SSP1_D6              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_D07__SSP1_D7              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CE0N__SSP3_D0             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CE1N__SSP3_D3             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CE2N__CAN1_TX             MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CE3N__CAN1_RX             MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT          MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDY1__SSP1_CMD                  MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDY2__CAN0_TX             MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDY3__CAN0_RX             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RDN__SSP3_SCK             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_WRN__SSP1_SCK             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_ALE__SSP3_D1              MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_CLE__SSP3_D2              MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
#define MX28_PAD_GPMI_RESETN__SSP3_CMD                MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)

#define MX28_PAD_LCD_D03__ETM_DA8               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D04__ETM_DA9               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D08__ETM_DA3               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D09__ETM_DA4               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN        MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN        MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
#define MX28_PAD_LCD_RD_E__LCD_VSYNC                  MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC                MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
#define MX28_PAD_LCD_RS__LCD_DOTCLK             MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
#define MX28_PAD_LCD_CS__LCD_ENABLE             MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0        MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1        MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK               MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)

#define MX28_PAD_SSP0_DATA4__SSP2_D0                  MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
#define MX28_PAD_SSP0_DATA5__SSP2_D3                  MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
#define MX28_PAD_SSP0_DATA6__SSP2_CMD                 MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
#define MX28_PAD_SSP0_DATA7__SSP2_SCK                 MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
#define MX28_PAD_SSP1_SCK__SSP2_D1              MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
#define MX28_PAD_SSP1_CMD__SSP2_D2              MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
#define MX28_PAD_SSP1_DATA0__SSP2_D6                  MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
#define MX28_PAD_SSP1_DATA3__SSP2_D7                  MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_SCK__AUART2_RX                  MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_MOSI__AUART2_TX                 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_MISO__AUART3_RX                 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_SS0__AUART3_TX                  MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_SS1__SSP2_D1              MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
#define MX28_PAD_SSP2_SS2__SSP2_D2              MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
#define MX28_PAD_SSP3_SCK__AUART4_TX                  MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
#define MX28_PAD_SSP3_MOSI__AUART4_RX                 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
#define MX28_PAD_SSP3_MISO__AUART4_RTS                MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
#define MX28_PAD_SSP3_SS0__AUART4_CTS                 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)

#define MX28_PAD_AUART0_RX__I2C0_SCL                  MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
#define MX28_PAD_AUART0_TX__I2C0_SDA                  MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
#define MX28_PAD_AUART0_CTS__AUART4_RX                MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
#define MX28_PAD_AUART0_RTS__AUART4_TX                MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT          MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT          MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT         MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
#define MX28_PAD_AUART1_RTS__USB0_ID                  MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
#define MX28_PAD_AUART2_RX__SSP3_D1             MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
#define MX28_PAD_AUART2_TX__SSP3_D2             MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
#define MX28_PAD_AUART2_CTS__I2C1_SCL                 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
#define MX28_PAD_AUART2_RTS__I2C1_SDA                 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
#define MX28_PAD_AUART3_RX__CAN0_TX             MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
#define MX28_PAD_AUART3_TX__CAN0_RX             MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
#define MX28_PAD_AUART3_CTS__CAN1_TX                  MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
#define MX28_PAD_AUART3_RTS__CAN1_RX                  MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
#define MX28_PAD_PWM0__I2C1_SCL                       MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
#define MX28_PAD_PWM1__I2C1_SDA                       MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
#define MX28_PAD_PWM2__USB0_ID                        MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
#define MX28_PAD_SAIF0_MCLK__PWM_3              MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
#define MX28_PAD_SAIF0_LRCLK__PWM_4             MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
#define MX28_PAD_SAIF0_BITCLK__PWM_5                  MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
#define MX28_PAD_SAIF0_SDATA0__PWM_6                  MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA       MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB       MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
#define MX28_PAD_SAIF1_SDATA0__PWM_7                  MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
#define MX28_PAD_LCD_RESET__LCD_VSYNC                 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)

#define MX28_PAD_ENET0_MDC__GPMI_CE4N                 MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_MDIO__GPMI_CE5N                MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N               MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RXD0__GPMI_CE7N                MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RXD1__GPMI_READY4        MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER          MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TX_EN__GPMI_READY5       MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TXD0__GPMI_READY6        MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TXD1__GPMI_READY7        MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RXD2__ENET1_RXD0               MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RXD3__ENET1_RXD1               MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TXD2__ENET1_TXD0               MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_TXD3__ENET1_TXD1               MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER            MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_COL__ENET1_TX_EN               MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
#define MX28_PAD_ENET0_CRS__ENET1_RX_EN               MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)

/* MUXSEL_2 */
#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER               MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK                MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_RDY0__USB0_ID             MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER               MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER       MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_ALE__SSP3_D4              MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
#define MX28_PAD_GPMI_CLE__SSP3_D5              MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)

#define MX28_PAD_LCD_D00__ETM_DA0               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D01__ETM_DA1               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D02__ETM_DA2               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D03__ETM_DA3               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D04__ETM_DA4               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D05__ETM_DA5               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D06__ETM_DA6               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D07__ETM_DA7               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D08__ETM_DA8               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D09__ETM_DA9               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D10__ETM_DA10              MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D11__ETM_DA11              MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D12__ETM_DA12              MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D13__ETM_DA13              MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D14__ETM_DA14              MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D15__ETM_DA15              MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D16__ETM_DA7               MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D17__ETM_DA6               MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D18__ETM_DA5               MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D19__ETM_DA4               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D20__ETM_DA3               MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D21__ETM_DA2               MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D22__ETM_DA1               MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
#define MX28_PAD_LCD_D23__ETM_DA0               MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
#define MX28_PAD_LCD_RD_E__ETM_TCTL             MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
#define MX28_PAD_LCD_WR_RWN__ETM_TCLK                 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
#define MX28_PAD_LCD_HSYNC__ETM_TCTL                  MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
#define MX28_PAD_LCD_DOTCLK__ETM_TCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)

#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT      MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN       MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN     MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1               MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2        MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1        MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2               MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT           MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT           MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT      MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN      MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT     MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)

#define MX28_PAD_AUART0_RX__DUART_CTS                 MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
#define MX28_PAD_AUART0_TX__DUART_RTS                 MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
#define MX28_PAD_AUART0_CTS__DUART_RX                 MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
#define MX28_PAD_AUART0_RTS__DUART_TX                 MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
#define MX28_PAD_AUART1_RX__PWM_0               MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
#define MX28_PAD_AUART1_TX__PWM_1               MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA           MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB           MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
#define MX28_PAD_AUART2_RX__SSP3_D4             MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
#define MX28_PAD_AUART2_TX__SSP3_D5             MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK       MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK        MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT     MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN      MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT    MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN     MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
#define MX28_PAD_PWM0__DUART_RX                       MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
#define MX28_PAD_PWM1__DUART_TX                       MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
#define MX28_PAD_PWM2__USB1_OVERCURRENT               MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
#define MX28_PAD_SAIF0_MCLK__AUART4_CTS               MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS        MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
#define MX28_PAD_SAIF0_BITCLK__AUART4_RX        MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
#define MX28_PAD_SAIF0_SDATA0__AUART4_TX        MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
#define MX28_PAD_I2C0_SCL__DUART_RX             MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
#define MX28_PAD_I2C0_SDA__DUART_TX             MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1           MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
#define MX28_PAD_SPDIF__ENET1_RX_ER             MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)

#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1        MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2       MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1            MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2       MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT  MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT    MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN     MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT    MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN     MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN   MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT     MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN      MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)

/* MUXSEL_GPIO */
#define MX28_PAD_GPMI_D00__GPIO_0_0             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D01__GPIO_0_1             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D02__GPIO_0_2             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D03__GPIO_0_3             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D04__GPIO_0_4             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D05__GPIO_0_5             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D06__GPIO_0_6             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_D07__GPIO_0_7             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CE0N__GPIO_0_16                 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CE1N__GPIO_0_17                 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CE2N__GPIO_0_18                 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CE3N__GPIO_0_19                 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDY0__GPIO_0_20                 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDY1__GPIO_0_21                 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDY2__GPIO_0_22                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDY3__GPIO_0_23                 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RDN__GPIO_0_24                  MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_WRN__GPIO_0_25                  MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_ALE__GPIO_0_26                  MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_CLE__GPIO_0_27                  MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
#define MX28_PAD_GPMI_RESETN__GPIO_0_28               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)

#define MX28_PAD_LCD_D00__GPIO_1_0              MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D01__GPIO_1_1              MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D02__GPIO_1_2              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D03__GPIO_1_3              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D04__GPIO_1_4              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D05__GPIO_1_5              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D06__GPIO_1_6              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D07__GPIO_1_7              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D08__GPIO_1_8              MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D09__GPIO_1_9              MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D10__GPIO_1_10             MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D11__GPIO_1_11             MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D12__GPIO_1_12             MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D13__GPIO_1_13             MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D14__GPIO_1_14             MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D15__GPIO_1_15             MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D16__GPIO_1_16             MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D17__GPIO_1_17             MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D18__GPIO_1_18             MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D19__GPIO_1_19             MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D20__GPIO_1_20             MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D21__GPIO_1_21             MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D22__GPIO_1_22             MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_D23__GPIO_1_23             MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_RD_E__GPIO_1_24                  MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_WR_RWN__GPIO_1_25                MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_RS__GPIO_1_26              MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_CS__GPIO_1_27              MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_VSYNC__GPIO_1_28                 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_HSYNC__GPIO_1_29                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_DOTCLK__GPIO_1_30                MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_ENABLE__GPIO_1_31                MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)

#define MX28_PAD_SSP0_DATA0__GPIO_2_0                 MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA1__GPIO_2_1                 MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA2__GPIO_2_2                 MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA3__GPIO_2_3                 MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA4__GPIO_2_4                 MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA5__GPIO_2_5                 MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA6__GPIO_2_6                 MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DATA7__GPIO_2_7                 MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_CMD__GPIO_2_8             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_DETECT__GPIO_2_9                MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP0_SCK__GPIO_2_10                  MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP1_SCK__GPIO_2_12                  MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP1_CMD__GPIO_2_13                  MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP1_DATA0__GPIO_2_14                MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP1_DATA3__GPIO_2_15                MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_SCK__GPIO_2_16                  MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_MOSI__GPIO_2_17                 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_MISO__GPIO_2_18                 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_SS0__GPIO_2_19                  MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_SS1__GPIO_2_20                  MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP2_SS2__GPIO_2_21                  MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP3_SCK__GPIO_2_24                  MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP3_MOSI__GPIO_2_25                 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP3_MISO__GPIO_2_26                 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
#define MX28_PAD_SSP3_SS0__GPIO_2_27                  MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)

#define MX28_PAD_AUART0_RX__GPIO_3_0                  MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART0_TX__GPIO_3_1                  MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART0_CTS__GPIO_3_2                 MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART0_RTS__GPIO_3_3                 MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART1_RX__GPIO_3_4                  MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART1_TX__GPIO_3_5                  MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART1_CTS__GPIO_3_6                 MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART1_RTS__GPIO_3_7                 MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART2_RX__GPIO_3_8                  MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART2_TX__GPIO_3_9                  MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART2_CTS__GPIO_3_10                MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART2_RTS__GPIO_3_11                MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART3_RX__GPIO_3_12                 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART3_TX__GPIO_3_13                 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART3_CTS__GPIO_3_14                MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
#define MX28_PAD_AUART3_RTS__GPIO_3_15                MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM0__GPIO_3_16                MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM1__GPIO_3_17                MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM2__GPIO_3_18                MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF0_MCLK__GPIO_3_20                MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21               MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22        MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23        MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
#define MX28_PAD_I2C0_SCL__GPIO_3_24                  MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
#define MX28_PAD_I2C0_SDA__GPIO_3_25                  MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26        MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
#define MX28_PAD_SPDIF__GPIO_3_27               MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM3__GPIO_3_28                MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
#define MX28_PAD_PWM4__GPIO_3_29                MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
#define MX28_PAD_LCD_RESET__GPIO_3_30                 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)

#define MX28_PAD_ENET0_MDC__GPIO_4_0                  MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_MDIO__GPIO_4_1                 MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RX_EN__GPIO_4_2                MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RXD0__GPIO_4_3                 MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RXD1__GPIO_4_4                 MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5               MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TX_EN__GPIO_4_6                MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TXD0__GPIO_4_7                 MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TXD1__GPIO_4_8                 MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RXD2__GPIO_4_9                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RXD3__GPIO_4_10                MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TXD2__GPIO_4_11                MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_TXD3__GPIO_4_12                MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13        MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_COL__GPIO_4_14                 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET0_CRS__GPIO_4_15                 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
#define MX28_PAD_ENET_CLK__GPIO_4_16                  MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
#define MX28_PAD_JTAG_RTCK__GPIO_4_20                 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)

#endif /* __MACH_IOMUX_MX28_H__ */

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